Strained Days Indeed

Without delving into exotica such as quantum and biological computing, Moore’s Law should continue for another 15 years.

By that time, though, transistors will be so small and tightly packed that they’ll consume huge amounts of electricity and require expensive cooling units, making them less useful for personal and mobile applications.

In particular, the power consumption problem (which is primarily an issue of leakage) could limit the processing power of laptops, smart phones and other battery-powered mobile devices upon which the industry’s technology scenarios depend. With the power-thrifty Dual Stress Liner (DSL) technology announced in December, Advanced Micro Devices and IBM have taken a big step toward ensuring that Moore’s Law applies to more than just the chips that run supercomputers.

By reducing the size of transistors and the silicon-covered spaces between them, fewer electrons leak away in transit when transistors are turned on. Because newer processors have far more transistors, though, this advantage is somewhat offset by the greater number of opportunities for leakage and the increase in static leakage, which is the power and heat drain that seeps away when all those transistors are turned off.

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Like other “strained silicon” processes, DSL stretches and compresses different portions of the silicon to improve current flow.

The immediate payoff lies in performance, with both companies claiming a 24 percent boost in transistor speed compared with the 15 to 20 percent gains with Intel’s current strained-silicon technology

And both AMD and IMB claim they can achieve these results without consuming more power or raising the production costs.

As with any processor, boosts in transistor speed are considerably larger than the real-world performance improvements you can expect in your next computer. Yet, in cases in which speed is prioritized over power savings, AMD expects gains of up to 16 percent in computers running its new DSL AMD64 processors due this summer. Similarly, IBM should deliver Power-Architecture processors with equal gains around the same time. Sony and Toshiba also participated in the development of the technology and may use it in the upcoming CELL processor which is designed for consumer electronics products.

Like Intel’s strained silicon, which was introduced in 2003, DSL overcomes the challenge posed by the split personality of computer processors, which are a hodgepodge of negative and positive transistors.

Negative transistors perform better when stretched, as the elongation of the silicon orbitals tends to iron out energy variations that could slow the path of electrons.  Positive transistors work better when compressed. Until recently, it has been difficult to apply the two types of treatments without favoring one transistor type over the other.

Instead of using the exotic silicon germanium, which others like Intel have done, AMD and IBM have managed to get by with the more familiar silicon nitride. By sticking with a conventional process, says Kepler, yield should be higher and costs lower.

“Silicon germanium is more costly and adds more complexity to the manufacturing flow,” he says. “There are many issues associated with it when you add materials or etch the cavity, and creating the strain is more complex.”

The DSL approach applies a compressive film over the entire chip and then etches the material away from the negative transistors. A tensile strain film is then applied universally and etched away from the P-type transistors.

For any given chip, strained-silicon chip makers can select an optimum tradeoff between power consumption and speed. With DSL, tuning for performance/power tradeoffs can be done at two stages.

 “During fabrication, we can make very slight changes, making the transition gates longer or thicker to reduce leakage,” Kepler says. “Or later we can turn down the voltage on the part.”

Either way, AMD and IBM promise to further improve power efficiency and reduce heat by integrating DSL with the duo’s previously introduced Silicon-On-Insulator technology, which adds a thin insulating layer between substrate layers to minimize leakage.

DSL technology is already being incorporated into older 130nm designs, and it will be added to AMD’s new 90nm dual-processor Opteron chips this fall. According to Kepler, DSL has been successfully tested with next-generation 65nm designs, and he expects it to work fine when they shrink their processors to 45nm, as well.

The AMD/IBM advantage may not last long. By the end of year, Intel should introduce its first 65nm processors, which include an improved form of germanium-based strained silicon that Intel claims will provide 30-percent speed increases over non-strained chips.

The basics of strained silicon technology have been known for over a decade, but warping silicon hasn’t been a priority because it was far easier to meet Moore’s Law by scaling down transistors. Beyond 45nm, however, it will become considerably trickier to gain the same performance improvements with consistent yield without undue power consumption and heat.

Yield is also an issue with strained silicon, as defects tend to crop up when you warp silicon. This may be particularly true with germanium. Texas Instruments, for example, is working on a strained silicon technology that uses the absolute minimum of germanium in order to reduce defects.

A year from now we should know whether Intel has solved the germanium yield problem or whether AMD and IBM were smart to stick with silicon nitride. For consumers, though, the important point is that semiconductor manufacturers are finally placing power efficiency at an equal priority as speed. After all, speed doesn’t matter if your battery runs out.